1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit (IC), and more particularly, to a apparatus and a method for outputting data in a semiconductor IC.
2. Related Art
In general, a semiconductor IC includes an apparatus to output a data signal ‘DQ’ and a data strobe signal ‘DQS’ indicative of timing for reading the data signal ‘DQ’ from an exterior of the semiconductor IC in response to a read command.
FIG. 1 is a schematic block diagram of a conventional data output apparatus of a semiconductor IC. In FIG. 1, the data output apparatus 10 includes latches 1 and 2 and drivers 3 and 4. A pre-data signal ‘PRE_DQ’ is latched by the latch 1 in response to a clock signal ‘CLKDO’ and is output as a data signal ‘DQ’ through the driver 3. In addition, a pre-data strobe signal ‘PRE_DQS’ is latched by the latch 2 in response to the clock signal ‘CLKDO’ and is output as a data strobe signal ‘DQS’ through the driver 4. The clock signal ‘CLKDO’ is a signal generated using a delay locked loop clock signal ‘DLLCLK’ during the activation interval of an output enable signal ‘OUTEN’.
FIG. 2 is a timing diagram illustrating the operation of the conventional data output apparatus of In FIG. 1. As can be seen, the output timing of the data signal ‘DQ’ and the data strobe signal ‘DQS’ is commonly determined by the clock signal ‘CLKDO’. The potential of a pad connected with the data signal ‘DQ’ according to termination operation is set to a termination voltage level ‘VTT’, i.e., to one-half of a power voltage level ‘VDDQ/2’.
In FIG. 2, the data signal ‘DQ’ transitions to a high level, i.e., ‘VDDQ’, or to a low level, i.e., ‘VSSQ’, from the termination level ‘VTT’. The potential of a pad connected with the data strobe signal ‘DQS’ is also set to the termination level ‘VTT’. Conversely, the data strobe signal ‘DQS’ transitions from a ground voltage level ‘VSSQ’ according to the preamble standards for semiconductor ICs. The preamble standards are defined to ensure that the data strobe signal ‘DQS’ is maintained at the ground voltage level ‘VSSQ’ for a time corresponding to one clock signal ‘CLK’ before the data strobe signal ‘DQS’ is initially generated.
As described above, although the data signal ‘DQ’ and the data strobe signal ‘DQS’ start to transition with the same clock signal ‘CLKDO’, the times required for the data signal ‘DQ’ and the data strobe signal ‘DQS’ to reach the termination level ‘VTT’ are different from each other due to the starting levels of the data signal ‘DQ’ and the data strobe signal ‘DQS’, which are different from each other. Thus, the data signal ‘DQ’ and the data strobe signal ‘DQS’ have a time difference to reach the termination level ‘VTT’. As the time difference becomes shorter, it is advantageous for the normal operation of the semiconductor IC. Although it is preferable that there is no time difference, in an actual circuit, the time difference is likely to deviate by a predefined specification ‘tLZ’.
If the mismatch between the data signal ‘DQ’ and the data strobe signal ‘DQS’ increases, i.e., as the time difference between the data signal ‘DQ’ and the data strobe signal ‘DQS’ deviates the predefined specification ‘tLZ’, an external system may not precisely recognize the data output from the semiconductor IC, thereby creating problems.